Half finished attempt to make the source scripts handle spaces in path names

(for instance for $BUILD_WORK).
Unfortunately, it probably won't be completely finished as long
as we keep using GNU make. It's just too far gone.


git-svn-id: svn://svn.code.sf.net/p/sc2/code/trunk@1346 8092fc87-c524-0410-9efc-e669fe64eaf9

sc2/Makefile.build

@@ -1,3 +1,6 @@
+# Make file for the uqm build system. Invoked from build/unix/build_functions
+# By Serge van den Boom
+
 default:
 	./build.sh sc2
 
@@ -6,19 +9,37 @@ default:
 	if [ ! -d $$DIR ]; then \
 		mkdir -p "$$DIR"; \
 	fi
-	$(WINDRES) --include-dir $(dir $<) -o $@ $<
+	$(WINDRES) --include-dir $(dir $<) -o "$@" "$<"
 
 %.o:
 	@DIR=$(dir $@); \
 	if [ ! -d $$DIR ]; then \
 		mkdir -p "$$DIR"; \
 	fi
-	$(COMPILE) -o $@ -c $(CFLAGS) $<
+	$(COMPILE) -o "$@" -c $(CFLAGS) "$<"
 
 target-%:
-	$(COMPILE) -o $* $^ $(LDFLAGS)
+	$(COMPILE) -o "$*" $^ $(LDFLAGS)
 
--include $(DEPEND_FILE)
+
+## The following kludge is necessary because the GNU make 'include'
+## statement does not accept spaces etc in the argument.
+#define ESCAPE_DEPEND
+#sed -e 's/["$$ 	#\*\?\\]/\\&/g' << EOF
+#$${DEPEND_FILE}
+#EOF
+#endef
+#export ESCAPE_DEPEND
+#.PHONY: escape_depend
+#.INTERMEDIATE: escape_depend
+#escape_depend:
+##	@set > set.out
+#	@sh -x -v -c "$$ESCAPE_DEPEND"
+#ifneq ($(MAKECMDGOALS),escape_depend)
+#include $(shell $(MAKE) -f Makefile.build escape_depend)
+#endif
+
+include $(DEPEND_FILE)
 
 # Temporary:
 $(BUILD_WORK)/obj/release/./src/res/UrQuanMasters.rc.o: \

sc2/build/unix/build.config

@@ -209,7 +209,7 @@ uqm_process_config() {
 
 	CFLAGS="$CFLAGS -I \"$BUILD_WORK\""
 
-	# Export the HAVE_ symbols to config_unix.h, using config_unix.h.ini
+	# Export the HAVE_ symbols to config_unix.h, using config_unix.h.in
 	# as template.
 	SUBSTITUTE_VARS="$HAVE_SYMBOLS CONTENTDIR"
 	SUBSTITUTE_FILES="config_unix.h"

sc2/build/unix/build_functions

@@ -35,6 +35,12 @@ usage() {
 	echo
 }
 
+escape_string() {
+	$PROG_sed_FILE -e s,[\\\'\"\`\	\ \$\&\\\*\\\?\#\!],\\\\\&,g << EOF
+$1
+EOF
+}
+
 # The actual recursing function
 build_recurse() {
 	local FILES SUBDIRS
@@ -64,7 +70,7 @@ build_do_recursive() {
 # Build dependancy information for one file
 build_dependancies() {
 	eval echo -n \$BUILD_WORK/\${${BUILD_PROJECT}_OBJS}\$BUILD_REC_PATH
-	eval \$MKDEPEND "\${${BUILD_PROJECT}_CFLAGS}" "\$1"
+	eval eval \\\$MKDEPEND \"\${${BUILD_PROJECT}_CFLAGS}\" \"\\\$1\"
 }
 
 # Recursively build dependancy information
@@ -72,6 +78,9 @@ build_rec_dependancies() {
 	local DEPEND_FILE EXTRA_OFILES
 
 	echo "Building dependancy information..." 1>&2
+	
+	BUILD_WORK_ESC=`escape_string "$BUILD_WORK"`
+	export BUILD_WORK_ESC
 
 	# Remove the old dependency file, if it exists.
 	# The .tmp file is used to detect interrupted dependency builds.
@@ -86,7 +95,7 @@ build_rec_dependancies() {
 
 	eval DEPEND_FILE="\$BUILD_WORK/.depend.\${${BUILD_PROJECT}_NAME}"
 	{
-		eval echo -n "\$BUILD_WORK/target-\${${BUILD_PROJECT}_NAME}:"
+		eval echo -n "\$BUILD_WORK_ESC/target-\${${BUILD_PROJECT}_NAME}:"
 		for OFILE in $OFILES $EXTRA_OFILES; do
 			echo -n " $OFILE"
 		done
@@ -98,18 +107,21 @@ build_rec_dependancies() {
 
 # Output the .o file for a .c file.
 build_collect_o_files() {
-	eval echo "\$BUILD_WORK/\${${BUILD_PROJECT}_OBJS}\${1%.c}.o"
+	eval echo "\$BUILD_WORK_ESC/\${${BUILD_PROJECT}_OBJS}\${1%.c}.o"
 }
 
 # Output the extra .o file with the complete path
 build_collect_extra_o_files() {
-	eval echo "\$BUILD_WORK/\${${BUILD_PROJECT}_OBJS}\$1"
+	eval echo "\$BUILD_WORK_ESC/\${${BUILD_PROJECT}_OBJS}\$1"
 }
 
 # Recursively collect .o-files
 build_rec_collect_o_files() {
 	local EXTRA_OFILES
 
+	BUILD_WORK_ESC=`escape_string "$BUILD_WORK"`
+	export BUILD_WORK_ESC
+
 	BUILD_FILES_VAR=${BUILD_PROJECT}_CFILES
 	export BUILD_FILES_VAR
 	build_do_recursive build_collect_o_files :
@@ -155,18 +167,18 @@ build_compile() {
 	eval CFLAGS="\${${BUILD_PROJECT}_CFLAGS}" \
 			LDFLAGS="\${${BUILD_PROJECT}_LDFLAGS}" \
 			DEPEND_FILE="\$BUILD_WORK/.depend.\${${BUILD_PROJECT}_NAME%/}" \
-			\$MAKE -f Makefile.build "\$BUILD_WORK/target-\${${BUILD_PROJECT}_NAME}"
+			\$MAKE -f Makefile.build \"\$BUILD_WORK/target-\${${BUILD_PROJECT}_NAME}\"
 	eval "${TARGET}_post_build"
 }
 
 # Description: Remove the .o file for one .c file
 # Arguments:   $1 - the .c file
 build_clean_file() {
-	eval rm -f -- "\$BUILD_WORK/\${${BUILD_PROJECT}_OBJS}\${1%.c}.o"
+	eval rm -f -- "\"\$BUILD_WORK/\${${BUILD_PROJECT}_OBJS}\${1%.c}.o\""
 }
 
 build_clean_dir() {
-	eval rmdir -- "\$BUILD_WORK/\${${BUILD_PROJECT}_OBJS}\${1}" 2> /dev/null
+	eval rmdir -- "\"\$BUILD_WORK/\${${BUILD_PROJECT}_OBJS}\${1}\"" 2> /dev/null
 	return 0
 }