adam/vim
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Update runtime files

Browse Source
This commit is contained in:
Bram Moolenaar
2020-04-10 22:10:56 +02:00
parent 7b293c730b
commit d1caa941d8
24 changed files with 187 additions and 88 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
runtime/syntax/vhdl.vim
View File

@ -3,7 +3,7 @@
" Maintainer: Daniel Kho <daniel.kho@logik.haus>
" Previous Maintainer: Czo <Olivier.Sirol@lip6.fr>
" Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn>
" Last Changed: 2020 Mar 09 by Daniel Kho
" Last Changed: 2020 Apr 04 by Daniel Kho
" quit when a syntax file was already loaded
if exists("b:current_syntax")
@ -16,10 +16,10 @@ set cpo&vim
" case is not significant
syn case ignore
" VHDL keywords
syn keyword vhdlStatement access after alias all assert
" VHDL 1076-2019 keywords
syn keyword vhdlStatement access after alias all
syn keyword vhdlStatement architecture array attribute
syn keyword vhdlStatement assume assume_guarantee
syn keyword vhdlStatement assert assume
syn keyword vhdlStatement begin block body buffer bus
syn keyword vhdlStatement case component configuration constant
syn keyword vhdlStatement context cover
@ -34,20 +34,19 @@ syn keyword vhdlStatement map
syn keyword vhdlStatement new next null
syn keyword vhdlStatement of on open others out
syn keyword vhdlStatement package port postponed procedure process pure
syn keyword vhdlStatement parameter property protected
syn keyword vhdlStatement parameter property protected private
syn keyword vhdlStatement range record register reject report return
syn keyword vhdlStatement release restrict restrict_guarantee
syn keyword vhdlStatement select severity signal shared
syn keyword vhdlStatement subtype
syn keyword vhdlStatement release restrict
syn keyword vhdlStatement select severity signal shared subtype
syn keyword vhdlStatement sequence strong
syn keyword vhdlStatement then to transport type
syn keyword vhdlStatement unaffected units until use
syn keyword vhdlStatement variable
" VHDL-2019 interface
syn keyword vhdlStatement view
syn keyword vhdlStatement vmode vprop vunit
syn keyword vhdlStatement variable view
syn keyword vhdlStatement vpkg vmode vprop vunit
syn keyword vhdlStatement wait when while with
syn keyword vhdlStatement note warning error failure
" VHDL predefined severity levels
syn keyword vhdlAttribute note warning error failure
" Linting of conditionals.
syn match vhdlStatement "\<\(if\|else\)\>"
@ -265,4 +264,5 @@ let b:current_syntax = "vhdl"
let &cpo = s:cpo_save
unlet s:cpo_save
" vim: ts=8