Update runtime files. Add support for J.
This commit is contained in:
Bram Moolenaar
@ -1,12 +1,12 @@
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" Vim syntax file
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" Language: VHDL
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" Maintainer: Czo <Olivier.Sirol@lip6.fr>
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" Maintainer: Daniel Kho <daniel.kho@tauhop.com>
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" Previous Maintainer: Czo <Olivier.Sirol@lip6.fr>
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" Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn>
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" Last Change: 2012 Jun 01
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" (Dominique Pelle added @Spell)
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" Last Changed: 2012 Feb 03 by Thilo Six
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" $Id: vhdl.vim,v 1.1 2004/06/13 15:34:56 vimboss Exp $
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" VHSIC Hardware Description Language
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" Very High Scale Integrated Circuit
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" VHSIC (Very High Speed Integrated Circuit) Hardware Description Language
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" For version 5.x: Clear all syntax items
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" For version 6.x: Quit when a syntax file was already loaded
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@ -22,8 +22,8 @@ set cpo&vim
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" This is not VHDL. I use the C-Preprocessor cpp to generate different binaries
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" from one VHDL source file. Unfortunately there is no preprocessor for VHDL
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" available. If you don't like this, please remove the following lines.
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syn match cDefine "^#ifdef[ ]\+[A-Za-z_]\+"
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syn match cDefine "^#endif"
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"syn match cDefine "^#ifdef[ ]\+[A-Za-z_]\+"
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"syn match cDefine "^#endif"
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" case is not significant
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syn case ignore
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@ -31,11 +31,14 @@ syn case ignore
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" VHDL keywords
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syn keyword vhdlStatement access after alias all assert
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syn keyword vhdlStatement architecture array attribute
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syn keyword vhdlStatement assume assume_guarantee
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syn keyword vhdlStatement begin block body buffer bus
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syn keyword vhdlStatement case component configuration constant
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syn keyword vhdlStatement disconnect downto
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syn keyword vhdlStatement context cover
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syn keyword vhdlStatement default disconnect downto
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syn keyword vhdlStatement elsif end entity exit
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syn keyword vhdlStatement file for function
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syn keyword vhdlStatement fairness force
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syn keyword vhdlStatement generate generic group guarded
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syn keyword vhdlStatement impure in inertial inout is
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syn keyword vhdlStatement label library linkage literal loop
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@ -43,12 +46,17 @@ syn keyword vhdlStatement map
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syn keyword vhdlStatement new next null
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syn keyword vhdlStatement of on open others out
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syn keyword vhdlStatement package port postponed procedure process pure
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syn keyword vhdlStatement parameter property protected
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syn keyword vhdlStatement range record register reject report return
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syn keyword vhdlStatement release restrict restrict_guarantee
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syn keyword vhdlStatement select severity signal shared
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syn keyword vhdlStatement subtype
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syn keyword vhdlStatement sequence strong
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syn keyword vhdlStatement then to transport type
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syn keyword vhdlStatement unaffected units until use
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syn keyword vhdlStatement variable wait when while with
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syn keyword vhdlStatement variable
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syn keyword vhdlStatement vmode vprop vunit
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syn keyword vhdlStatement wait when while with
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syn keyword vhdlStatement note warning error failure
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" Special match for "if" and "else" since "else if" shouldn't be highlighted.
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@ -60,6 +68,7 @@ syn match vhdlNone "\<else\s\+if\>\s"
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" Predefined VHDL types
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syn keyword vhdlType bit bit_vector
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syn keyword vhdlType character boolean integer real time
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syn keyword vhdlType boolean_vector integer_vector real_vector time_vector
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syn keyword vhdlType string severity_level
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" Predefined standard ieee VHDL types
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syn keyword vhdlType positive natural signed unsigned
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@ -67,11 +76,11 @@ syn keyword vhdlType line text
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syn keyword vhdlType std_logic std_logic_vector
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syn keyword vhdlType std_ulogic std_ulogic_vector
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" Predefined non standard VHDL types for Mentor Graphics Sys1076/QuickHDL
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syn keyword vhdlType qsim_state qsim_state_vector
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syn keyword vhdlType qsim_12state qsim_12state_vector
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syn keyword vhdlType qsim_strength
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"syn keyword vhdlType qsim_state qsim_state_vector
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"syn keyword vhdlType qsim_12state qsim_12state_vector
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"syn keyword vhdlType qsim_strength
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" Predefined non standard VHDL types for Alliance VLSI CAD
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syn keyword vhdlType mux_bit mux_vector reg_bit reg_vector wor_bit wor_vector
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"syn keyword vhdlType mux_bit mux_vector reg_bit reg_vector wor_bit wor_vector
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" array attributes
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syn match vhdlAttribute "\'high"
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@ -122,14 +131,14 @@ syn case match
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" Values for standard VHDL types
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syn match vhdlVector "\'[0L1HXWZU\-\?]\'"
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" Values for non standard VHDL types qsim_12state for Mentor Graphics Sys1076/QuickHDL
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syn keyword vhdlVector S0S S1S SXS S0R S1R SXR S0Z S1Z SXZ S0I S1I SXI
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"syn keyword vhdlVector S0S S1S SXS S0R S1R SXR S0Z S1Z SXZ S0I S1I SXI
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syn case ignore
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syn match vhdlVector "B\"[01_]\+\""
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syn match vhdlVector "O\"[0-7_]\+\""
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syn match vhdlVector "X\"[0-9a-f_]\+\""
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syn match vhdlCharacter "'.'"
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syn region vhdlString start=+"+ end=+"+ contains=@Spell
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syn region vhdlString start=+"+ end=+"+
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" floating numbers
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syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>"
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@ -151,9 +160,15 @@ syn match vhdlSpecial "[().,;]"
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syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>"
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syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>"
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syn match vhdlComment "--.*$" contains=@Spell
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syn keyword vhdlTodo contained TODO FIXME
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syn region vhdlComment start="/\*" end="\*/" contains=vhdlTodo,@Spell
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syn match vhdlComment "--.*" contains=vhdlTodo,@Spell
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" syn match vhdlGlobal "[\'$#~!%@?\^\[\]{}\\]"
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"Modify the following as needed. The trade-off is performance versus functionality.
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syn sync minlines=200
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" Define the default highlighting.
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" For version 5.7 and earlier: only when not done already
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" For version 5.8 and later: only when an item doesn't have highlighting yet
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@ -165,19 +180,20 @@ if version >= 508 || !exists("did_vhdl_syntax_inits")
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command -nargs=+ HiLink hi def link <args>
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endif
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HiLink cDefine PreProc
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" HiLink cDefine PreProc
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HiLink vhdlSpecial Special
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HiLink vhdlStatement Statement
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HiLink vhdlCharacter String
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HiLink vhdlCharacter Character
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HiLink vhdlString String
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HiLink vhdlVector String
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HiLink vhdlBoolean String
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HiLink vhdlVector Number
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HiLink vhdlBoolean Number
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HiLink vhdlTodo Todo
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HiLink vhdlComment Comment
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HiLink vhdlNumber String
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HiLink vhdlTime String
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HiLink vhdlNumber Number
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HiLink vhdlTime Number
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HiLink vhdlType Type
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HiLink vhdlOperator Type
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HiLink vhdlGlobal Error
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HiLink vhdlOperator Special
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" HiLink vhdlGlobal Error
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HiLink vhdlAttribute Type
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delcommand HiLink
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