updated for version 7.1a
This commit is contained in:
Bram Moolenaar
@ -1,8 +1,8 @@
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" VHDL indent ('93 syntax)
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" Language: VHDL
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" Maintainer: Gerald Lai <laigera+vim?gmail.com>
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" Version: 1.36
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" Last Change: 2006 Apr 12
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" Version: 1.50
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" Last Change: 2007 Jan 29
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" URL: http://www.vim.org/scripts/script.php?script_id=1450
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" only load this indent file when no other was loaded
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@ -13,9 +13,11 @@ let b:did_indent = 1
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" setup indent options for local VHDL buffer
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setlocal indentexpr=GetVHDLindent()
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setlocal indentkeys=!^F,o,O,e,0(,0)
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setlocal indentkeys=!^F,o,O,0(,0)
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setlocal indentkeys+==~begin,=~end\ ,=~end\ ,=~is,=~select,=~when
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setlocal indentkeys+==~if,=~then,=~elsif,=~else
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setlocal indentkeys+==~begin,=~is,=~select
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setlocal indentkeys+==~case,=~loop,=~for,=~generate,=~record,=~units,=~process,=~block,=~function,=~component,=~procedure
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setlocal indentkeys+==~architecture,=~configuration,=~entity,=~package
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" constants
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" not a comment
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@ -25,6 +27,16 @@ let s:ES = '\s*\%(--.*\)\=$'
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" no "end" keyword in front
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let s:NE = '\%(\<end\s\+\)\@<!'
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" option to disable alignment of generic/port mappings
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if !exists("g:vhdl_align_genportmap")
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let g:vhdl_align_genportmap = 1
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endif
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" option to disable alignment of right-hand side assignment "<=" statements
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if !exists("g:vhdl_align_rhsassign")
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let g:vhdl_align_rhsassign = 1
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endif
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" only define indent function once
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if exists("*GetVHDLindent")
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finish
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@ -100,7 +112,11 @@ function GetVHDLindent()
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if m != -1
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return m
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else
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return stridx(prevs, '(') + &sw
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if g:vhdl_align_genportmap
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return stridx(prevs, '(') + &sw
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else
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return ind2 + &sw
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endif
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endif
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endif
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@ -108,7 +124,11 @@ function GetVHDLindent()
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" keywords: variable + "<=" without ";" ending
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" where: start of previous line
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if prevs =~? '^\s*\S\+\s*<=[^;]*'.s:ES
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return matchend(prevs, '<=\s*\ze.')
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if g:vhdl_align_rhsassign
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return matchend(prevs, '<=\s*\ze.')
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else
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return ind2 + &sw
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endif
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endif
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" indent: backtrace previous non-comment lines for next smaller or equal size indent
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@ -190,7 +210,7 @@ function GetVHDLindent()
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" find previous opening statement of
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" keywords: "architecture", "block", "entity", "function", "generate", "procedure", "process"
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let s2 = s:NC.s:NE.'\<\%(architecture\|block\|entity\|function\|generate\|procedure\|process\)\>'
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if curs !~? s2.'.*'.s:NC.'\<begin\>.*'.s:ES && prevs =~? s2
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if (curs !~? s2.'.*'.s:NC.'\<begin\>.*'.s:ES && prevs =~? s2) || m == 1
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let ind = ind + &sw
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endif
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return ind
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@ -240,50 +260,55 @@ function GetVHDLindent()
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" where: start of current line
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" find previous opening statement of
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" keywords: "for", "if"
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if curs =~? '^\s*\<generate\>' && prevs =~? s:NC.s:NE.'\%(\%(\<wait\s\+\)\@<!\<for\>\|\<if\>\)'
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if curs =~? '^\s*\<generate\>' && prevs =~? s:NC.s:NE.'\%(\%(\<wait\s\+\)\@<!\<for\|\<if\)\>'
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return ind2
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endif
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" indent: +sw
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" keywords: "begin", "block", "loop", "process", "record", "units"
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" removed: "case", "elsif", "if", "while"
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" keywords: "block", "process"
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" removed: "begin", "case", "elsif", "if", "loop", "record", "units", "while"
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" where: anywhere in previous line
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if prevs =~? s:NC.'\%(\<begin\>\|'.s:NE.'\<\%(block\|loop\|process\|record\|units\)\>\)'
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if prevs =~? s:NC.s:NE.'\<\%(block\|process\)\>'
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return ind + &sw
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endif
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" indent: +sw
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" keywords: "architecture", "component", "configuration", "entity", "for", "package"
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" removed: "when", "with"
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" keywords: "architecture", "configuration", "entity", "package"
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" removed: "component", "for", "when", "with"
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" where: start of previous line
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if prevs =~? '^\s*\%(architecture\|component\|configuration\|entity\|for\|package\)\>'
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if prevs =~? '^\s*\%(architecture\|configuration\|entity\|package\)\>'
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return ind + &sw
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endif
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" indent: +sw
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" keyword: "generate", "is", "select", "=>"
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" keyword: "select"
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" removed: "generate", "is", "=>"
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" where: end of previous line
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if prevs =~? s:NC.'\%(\%('.s:NE.'\<generate\|\<is\|\<select\)\|=>\)'.s:ES
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if prevs =~? s:NC.'\<select'.s:ES
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return ind + &sw
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endif
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" indent: +sw
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" keyword: "else"
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" keyword: "begin", "loop", "record", "units"
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" where: anywhere in previous line
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" keyword: "component", "else", "for"
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" where: start of previous line
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" keyword: "then"
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" keyword: "generate", "is", "then", "=>"
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" where: end of previous line
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" _note_: indent allowed to leave this filter
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if prevs =~? '^\s*else\>' || prevs =~? s:NC.'\<then'.s:ES
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if prevs =~? s:NC.'\%(\<begin\>\|'.s:NE.'\<\%(loop\|record\|units\)\>\)' || prevs =~? '^\s*\%(component\|else\|for\)\>' || prevs =~? s:NC.'\%('.s:NE.'\<generate\|\<\%(is\|then\)\|=>\)'.s:ES
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let ind = ind + &sw
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endif
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" ****************************************************************************************
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" indent: -sw
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" keywords: "when", provided previous line does not begin with "when"
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" keywords: "when", provided previous line does not begin with "when", does not end with "is"
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" where: start of current line
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let s4 = '^\s*when\>'
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if curs =~? s4
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if prevs !~? s4
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if prevs =~? s:NC.'\<is'.s:ES
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return ind
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elseif prevs !~? s4
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return ind - &sw
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else
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return ind2
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@ -291,42 +316,9 @@ function GetVHDLindent()
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endif
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" indent: -sw
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" keywords: "else", "elsif", provided previous line does not contain "then"
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" keywords: "else", "elsif", "end" + "block", "for", "function", "generate", "if", "loop", "procedure", "process", "record", "units"
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" where: start of current line
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if curs =~? '^\s*\%(else\|elsif\)\>'
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if prevs !~? s:NC.'\<then\>'
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return ind - &sw
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else
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return ind2
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endif
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endif
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" indent: -sw
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" keywords: "end" + "if", provided previous line does not begin with "else", not contain "then"
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" where: start of current line
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if curs =~? '^\s*end\s\+if\>'
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if prevs !~? '^\s*else\>' && prevs !~? s:NC.'\<then\>'
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return ind - &sw
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else
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return ind2
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endif
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endif
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" indent: -sw
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" keywords: "end" + "function", "procedure", provided previous line does not contain "begin"
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" where: start of current line
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if curs =~? '^\s*end\s\+\%(function\|procedure\)\>'
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if prevs !~? s:NC.'\<begin\>'
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return ind - &sw
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else
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return ind2
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endif
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endif
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" indent: -sw
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" keywords: "end" + "block", "for", "generate", "loop", "process", "record", "units"
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" where: start of current line
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if curs =~? '^\s*end\s\+\%(block\|for\|generate\|loop\|process\|record\|units\)\>'
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if curs =~? '^\s*\%(else\|elsif\|end\s\+\%(block\|for\|function\|generate\|if\|loop\|procedure\|process\|record\|units\)\)\>'
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return ind - &sw
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endif
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@ -365,9 +357,9 @@ function GetVHDLindent()
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endif
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"indent: follow
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"keyword: "component"
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"where: anywhere in previous non-comment line
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"where: start of previous non-comment line
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elseif m == 2
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if ps =~? s:NC.s:NE.'\<component\>'
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if ps =~? '^\s*component\>'
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return indent(pn)
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endif
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endif
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@ -395,7 +387,8 @@ function GetVHDLindent()
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" indent: -sw
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" keywords: "end" + identifier
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" where: start of current line
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if curs =~? '^\s*end\s\+\w\+\>'
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"if curs =~? '^\s*end\s\+\w\+\>'
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if curs =~? '^\s*end\s'
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return ind - &sw
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endif
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