patch 9.0.1478: filetypes for *.v files not detected properly
Problem: Filetypes for *.v files not detected properly.
Solution: Use the file contents to detect the filetype. (Turiiya,
closes #12281)
This commit is contained in:
35
runtime/autoload/dist/ft.vim
vendored
35
runtime/autoload/dist/ft.vim
vendored
@ -1106,5 +1106,40 @@ export def FTlsl()
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endif
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endif
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enddef
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enddef
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# Set the filetype of a *.v file to Verilog, V or Cog based on the first 200
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# lines.
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export def FTv()
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if did_filetype()
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# ":setf" will do nothing, bail out early
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return
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endif
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for line in getline(1, 200)
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if line[0] =~ '^\s*/'
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# skip comment line
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continue
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endif
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# Verilog: line ends with ';' followed by an optional variable number of
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# spaces and an optional start of a comment.
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# Example: " b <= a + 1; // Add 1".
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if line =~ ';\(\s*\)\?\(/.*\)\?$'
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setf verilog
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return
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endif
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# Coq: line ends with a '.' followed by an optional variable number of
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# spaces and an optional start of a comment.
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# Example: "Definition x := 10. (*".
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if line =~ '\.\(\s*\)\?\((\*.*\)\?$'
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setf coq
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return
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endif
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endfor
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# No line matched, fall back to "v".
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setf v
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enddef
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# Uncomment this line to check for compilation errors early
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# Uncomment this line to check for compilation errors early
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# defcompile
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# defcompile
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@ -2303,8 +2303,8 @@ au BufNewFile,BufRead *.vr,*.vri,*.vrh setf vera
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" Vagrant (uses Ruby syntax)
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" Vagrant (uses Ruby syntax)
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au BufNewFile,BufRead Vagrantfile setf ruby
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au BufNewFile,BufRead Vagrantfile setf ruby
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" Verilog HDL
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" Verilog HDL, V or Coq
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au BufNewFile,BufRead *.v setf verilog
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au BufNewFile,BufRead *.v call dist#ft#FTv()
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" Verilog-AMS HDL
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" Verilog-AMS HDL
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au BufNewFile,BufRead *.va,*.vams setf verilogams
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au BufNewFile,BufRead *.va,*.vams setf verilogams
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@ -646,7 +646,6 @@ let s:filename_checks = {
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\ 'vdmrt': ['file.vdmrt'],
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\ 'vdmrt': ['file.vdmrt'],
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\ 'vdmsl': ['file.vdm', 'file.vdmsl'],
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\ 'vdmsl': ['file.vdm', 'file.vdmsl'],
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\ 'vera': ['file.vr', 'file.vri', 'file.vrh'],
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\ 'vera': ['file.vr', 'file.vri', 'file.vrh'],
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\ 'verilog': ['file.v'],
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\ 'verilogams': ['file.va', 'file.vams'],
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\ 'verilogams': ['file.va', 'file.vams'],
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\ 'vgrindefs': ['vgrindefs'],
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\ 'vgrindefs': ['vgrindefs'],
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\ 'vhdl': ['file.hdl', 'file.vhd', 'file.vhdl', 'file.vbe', 'file.vst', 'file.vhdl_123', 'file.vho', 'some.vhdl_1', 'some.vhdl_1-file'],
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\ 'vhdl': ['file.hdl', 'file.vhd', 'file.vhdl', 'file.vbe', 'file.vst', 'file.vhdl_123', 'file.vho', 'some.vhdl_1', 'some.vhdl_1-file'],
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@ -1771,6 +1770,27 @@ func Test_ttl_file()
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filetype off
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filetype off
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endfunc
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endfunc
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func Test_v_file()
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filetype on
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call writefile(['module tb; // Looks like a Verilog'], 'Xfile.v', 'D')
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split Xfile.v
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call assert_equal('verilog', &filetype)
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bwipe!
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call writefile(['module main'], 'Xfile.v')
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split Xfile.v
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call assert_equal('v', &filetype)
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bwipe!
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call writefile(['Definition x := 10. (*'], 'Xfile.v')
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split Xfile.v
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call assert_equal('coq', &filetype)
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bwipe!
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filetype off
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endfunc
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func Test_xpm_file()
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func Test_xpm_file()
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filetype on
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filetype on
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@ -695,6 +695,8 @@ static char *(features[]) =
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static int included_patches[] =
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static int included_patches[] =
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{ /* Add new patch number below this line */
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{ /* Add new patch number below this line */
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/**/
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1478,
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/**/
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/**/
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1477,
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1477,
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/**/
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/**/
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