Update runtime files.
This commit is contained in:
Bram Moolenaar
@ -1,14 +1,10 @@
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" Vim syntax file
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" Language: VHDL
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" Maintainer: Daniel Kho <daniel.kho@tauhop.com>
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" Language: VHDL [VHSIC (Very High Speed Integrated Circuit) Hardware Description Language]
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" Maintainer: Daniel Kho <daniel.kho@tauhop.com>
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" Previous Maintainer: Czo <Olivier.Sirol@lip6.fr>
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" Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn>
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" Last Changed: 2015 Dec 4 by Daniel Kho
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" Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn>
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" Last Changed: 2016 Mar 05 by Daniel Kho
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" VHSIC (Very High Speed Integrated Circuit) Hardware Description Language
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" For version 5.x: Clear all syntax items
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" For version 6.x: Quit when a syntax file was already loaded
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if version < 600
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syntax clear
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elseif exists("b:current_syntax")
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@ -56,17 +52,40 @@ syn keyword vhdlStatement note warning error failure
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syn match vhdlStatement "\<\(if\|else\)\>"
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syn match vhdlError "\<else\s\+if\>"
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" Predefined VHDL types
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syn keyword vhdlType bit bit_vector
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syn keyword vhdlType character boolean integer real time
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syn keyword vhdlType boolean_vector integer_vector real_vector time_vector
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syn keyword vhdlType string severity_level
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" Predefined standard ieee VHDL types
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syn keyword vhdlType positive natural signed unsigned
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syn keyword vhdlType unresolved_signed unresolved_unsigned u_signed u_unsigned
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syn keyword vhdlType line text
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syn keyword vhdlType std_logic std_logic_vector
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syn keyword vhdlType std_ulogic std_ulogic_vector
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" Types and type qualifiers
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" Predefined standard VHDL types
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syn match vhdlType "bit[\']*"
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syn match vhdlType "boolean[\']*"
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syn match vhdlType "natural[\']*"
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syn match vhdlType "positive[\']*"
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syn match vhdlType "integer[\']*"
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syn match vhdlType "real[\']*"
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syn match vhdlType "time[\']*"
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syn match vhdlType "bit_vector[\']*"
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syn match vhdlType "boolean_vector[\']*"
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syn match vhdlType "integer_vector[\']*"
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syn match vhdlType "real_vector[\']*"
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syn match vhdlType "time_vector[\']*"
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syn match vhdlType "character[\']*"
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syn match vhdlType "string[\']*"
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"syn keyword vhdlType severity_level
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syn match vhdlType "line[\']*"
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syn match vhdlType "text[\']*"
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" Predefined standard IEEE VHDL types
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syn match vhdlType "std_ulogic[\']*"
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syn match vhdlType "std_logic[\']*"
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syn match vhdlType "std_ulogic_vector[\']*"
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syn match vhdlType "std_logic_vector[\']*"
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syn match vhdlType "unresolved_signed[\']*"
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syn match vhdlType "unresolved_unsigned[\']*"
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syn match vhdlType "u_signed[\']*"
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syn match vhdlType "u_unsigned[\']*"
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syn match vhdlType "signed[\']*"
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syn match vhdlType "unsigned[\']*"
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" array attributes
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syn match vhdlAttribute "\'high"
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@ -191,15 +210,23 @@ syn case ignore
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syn region vhdlComment start="/\*" end="\*/" contains=vhdlTodo,vhdlFixme,@Spell
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syn match vhdlComment "\(^\|\s\)--.*" contains=vhdlTodo,vhdlFixme,@Spell
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" Standard IEEE P1076.6 preprocessor directives (metacomments).
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syn match vhdlPreProc "/\*\s*rtl_synthesis\s\+\(on\|off\)\s*\*/"
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syn match vhdlPreProc "\(^\|\s\)--\s*rtl_synthesis\s\+\(on\|off\)\s*"
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syn match vhdlPreProc "/\*\s*rtl_syn\s\+\(on\|off\)\s*\*/"
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syn match vhdlPreProc "\(^\|\s\)--\s*rtl_syn\s\+\(on\|off\)\s*"
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" Industry-standard directives. These are not standard VHDL, but are commonly
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" used in the industry.
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syn match vhdlPreProc "/\*\s*synthesis\s\+translate_\(on\|off\)\s*\*/"
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"syn match vhdlPreProc "/\*\s*simulation\s\+translate_\(on\|off\)\s*\*/"
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syn match vhdlPreProc "/\*\s*pragma\s\+translate_\(on\|off\)\s*\*/"
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syn match vhdlPreProc "/\*\s*pragma\s\+synthesis_\(on\|off\)\s*\*/"
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syn match vhdlPreProc "/\*\s*synopsys\s\+translate_\(on\|off\)\s*\*/"
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syn match vhdlPreProc "\(^\|\s\)--\s*synthesis\s\+translate_\(on\|off\)\s*"
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"syn match vhdlPreProc "\(^\|\s\)--\s*simulation\s\+translate_\(on\|off\)\s*"
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syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+translate_\(on\|off\)\s*"
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syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+synthesis_\(on\|off\)\s*"
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syn match vhdlPreProc "\(^\|\s\)--\s*synopsys\s\+translate_\(on\|off\)\s*"
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@ -216,24 +243,24 @@ if version >= 508 || !exists("did_vhdl_syntax_inits")
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else
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command -nargs=+ HiLink hi def link <args>
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endif
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HiLink vhdlSpecial Special
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HiLink vhdlStatement Statement
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HiLink vhdlCharacter Character
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HiLink vhdlString String
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HiLink vhdlVector Number
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HiLink vhdlBoolean Number
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HiLink vhdlTodo Todo
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HiLink vhdlFixme Fixme
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HiLink vhdlComment Comment
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HiLink vhdlNumber Number
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HiLink vhdlTime Number
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HiLink vhdlType Type
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HiLink vhdlOperator Operator
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HiLink vhdlError Error
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HiLink vhdlAttribute Special
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HiLink vhdlPreProc PreProc
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HiLink vhdlSpecial Special
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HiLink vhdlStatement Statement
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HiLink vhdlCharacter Character
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HiLink vhdlString String
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HiLink vhdlVector Number
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HiLink vhdlBoolean Number
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HiLink vhdlTodo Todo
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HiLink vhdlFixme Fixme
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HiLink vhdlComment Comment
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HiLink vhdlNumber Number
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HiLink vhdlTime Number
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HiLink vhdlType Type
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HiLink vhdlOperator Operator
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HiLink vhdlError Error
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HiLink vhdlAttribute Special
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HiLink vhdlPreProc PreProc
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delcommand HiLink
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endif
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