runtime(systemverilog): Add syntax highlighting for 1800-2023 block strings

closes: #18056

Signed-off-by: Ayan Banerjee <ayanbanrj@gmail.com>
Signed-off-by: Christian Brabandt <cb@256bit.org>
This commit is contained in:
Ayan Banerjee
2025-08-20 22:19:04 +02:00
committed by Christian Brabandt
parent d839a5b3b0
commit 014d50df80

View File

@ -1,7 +1,8 @@
" Vim syntax file " Vim syntax file
" Language: SystemVerilog " Language: SystemVerilog
" Maintainer: kocha <kocha.lsifrontend@gmail.com> " Maintainer: kocha <kocha.lsifrontend@gmail.com>
" Last Change: 12-Aug-2013. " Last Change: 12-Aug-2013.
" 2025 Aug 20 by Vim project: Add IEE1800-2023 block #18056
" quit when a syntax file was already loaded " quit when a syntax file was already loaded
if exists("b:current_syntax") if exists("b:current_syntax")
@ -68,6 +69,9 @@ syn keyword systemverilogConditional unique0
syn keyword systemverilogStatement implements syn keyword systemverilogStatement implements
syn keyword systemverilogStatement interconnect soft nettype syn keyword systemverilogStatement interconnect soft nettype
" IEEE1800-2023 add
syn region systemverilogBlockString start=+"""+ end=+"""+ contains=verilogEscape,@Spell
" Define the default highlighting. " Define the default highlighting.
" The default highlighting. " The default highlighting.
@ -78,6 +82,7 @@ hi def link systemverilogRepeat Repeat
hi def link systemverilogLabel Label hi def link systemverilogLabel Label
hi def link systemverilogGlobal Define hi def link systemverilogGlobal Define
hi def link systemverilogNumber Number hi def link systemverilogNumber Number
hi def link systemverilogBlockString String
let b:current_syntax = "systemverilog" let b:current_syntax = "systemverilog"